Title Page

Message from the Chairs

Reducing Parallelizing Compilation Time by Removing Redundant Analysis
Jixin Han, Rina Fujino, Ryota Tamura, Mamoru Shimaoka, Hiroki Mikami, Moriyuki Takamura, Sachio Kamiya, Kazuhiko Suzuki, Takahiro Miyajima, Keiji Kimura, and Hironori Kasahara
(Waseda University, Japan; OSCAR TECHNOLOGY, Japan)

A Divide-and-Conquer Parallel Pattern Implementation for Multicores
Marco Danelutto, Tiziano De Matteis, Gabriele Mencagli, and Massimo Torquati
(University of Pisa, Italy)

Parallel Evaluation of a DSP Algorithm using Julia
Peter Kourzanov
(NXP, Netherlands; Delft University of Technology, Netherlands)

Exhaustive Analysis of Thread-Level Speculation
Clark Verbrugge, Christopher J. F. Pickett, Alexander Krolik, and Allan Kielstra
(McGill University, Canada; IBM, Canada)